This application claims priority under 35 U.S.C. xc2xa7119 from Korean Patent Application No. 2001-72590, filed on Nov. 21, 2001, the entirety of which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a data output method and data output circuit, and more particularly, to a data output method and data output circuit capable of increasing data output speed by reducing clock power while increasing sensing speed.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a sense amplifier employing a flip-flop. Referring to FIG. 1, a Sense Amplifier Based Flip-Flop (SAFF) 100 comprises a master latch 10 and a slave latch 30. The master latch 10 comprises a cross coupled sense amplifier and the slave latch 30 comprises an R-S latch.
The SAFF 100 receives differential input signals (D and /D) and outputs differential output signals (Q and /Q). When a clock signal (CLK) is at a xe2x80x9clowxe2x80x9d logic level, the SAFF 100 is precharged, and when the clock signal (CLK) is at a xe2x80x9chighxe2x80x9d logic level, the SAFF 100 senses data (D and /D) and outputs data at a CMOS level.
Generally, the SAFF 100 consumes clock power (Pcp) and dynamic power (Pdp). The clock power and the dynamic power are expressed by the following equations 1 and 2, respectively:
Pcp=Ccxc3x97Vc2xc3x97fcxe2x80x83xe2x80x83(1) 
Here, Cc denotes the loading of the clock signal (CLK), Vc denotes the amplitude of the clock signal (CLK), and fc denotes the frequency of the clock signal (CLK).
Pdp=Ctcxc3x97V2xc3x97fxe2x80x83xe2x80x83(2) 
Here, Ctc denotes the total capacitance of internal nodes (/R, /S) in transition, V denotes the width of voltage swing of the internal nodes, and f denotes the transition frequency.
It is desired to reduce the clock power (Pcp). However, the clock power (Pcp) of the system increases as the clock loading increases. Therefore, it is a problem that the clock power (Pcp) of the SAFF 100 cannot be reduced.
FIG. 2 is a circuit diagram of a reduced clock swing flip-flop. The Reduced Clock Swing Flip-Flop (RCSFF) 200 of FIG. 2 uses a clock voltage lower than a supply voltage (VDD) in order to reduce the clock power (Pcp). The clock voltage means the amplitude of the clock signal (CLK). Referring to FIG. 2, the RCSFF 200 comprises a master latch 210 and a slave latch 230. While the RCSFF 200 is precharged, nodes (P and /P) are precharged to the supply voltage (VDD), and the gate voltages of precharge transistors (P1 and P2) are lower than the supply voltage (VDD). As a result, the leakage current of the precharge transistors (P1 and P2) increases. Therefore, in order to reduce the leakage current, the threshold voltage of the precharge transistors must be increased.
To increase the threshold voltage, a bulk voltage (Vwell) higher than the supply voltage (VDD) should be provided to the bulk of precharge transistors (P1 and P2).
To solve the above problems, it is an objective of the present invention to provide a data output method and data output circuit capable of increasing data output speed by reducing clock power while increasing sensing speed.
Accordingly, to accomplish the objective of the present invention, there is provided a data output method including (a) precharging output terminals to a precharge voltage lower than a supply voltage; and (b) outputting differential output signals to the output terminals in response to differential input signals.
It is preferable that in step (a) the output terminals are precharged in response to a clock signal of a first state, and in step (b) the differential signals are output to the output terminals in response to a clock signal of a second state.
Beneficially, the voltage or swing width of the clock signal is set lower than the precharge voltage.
Beneficially, the method further includes latching the differential output signals.
Also, there is provided a data output method including: (a) precharging output terminals to a first voltage lower than a supply voltage, in response to a clock signal of a first state; and (b) converting received first differential output signals into second differential output signals, in response to a clock signal of a second state, and outputting the converted signals to the output terminals.
Beneficially, the method further includes providing the clock signal at a second voltage lower than the first voltage
Further, there is provided a data output method, including precharging output terminals to a precharge voltage lower than a supply voltage, in a precharge phase; and outputting differential output signals to the output terminals in response to differential input signals, in an evaluation phase.
Still further, there is provided a data output circuit which outputs a differential output signal to output terminals, includes a precharge circuit that precharges the output terminals to a precharge voltage lower than a supply voltage; and an output circuit that outputs the differential output signals to the output terminals in response to differential input signals.
Beneficially, the precharge circuit precharges the output terminals in response to a clock signal of a first state, and the output circuit outputs the differential output signals to the output terminals in response to a clock signal of a second state.
Beneficially, the voltage of the clock signal is lower than the precharge voltage.
Beneficially, the circuit further includes a latch circuit that latches the differential output signals.
Yet further, there is provided a data output circuit that outputs a differential output signal to output terminals, includes a precharge circuit which precharges the output terminals to a precharge voltage lower than a supply voltage, in response to a clock signal of a first state; and an output circuit that outputs the differential output signals to the output terminals, in response to the clock signal of a second state.
Beneficially, the voltage of the clock signal is lower than the precharge voltage.
Beneficially, the circuit further includes a latch circuit which latches the differential output signals.
Moreover, there is provided a data output circuit with a flip-flop having a master latch and a slave latch, in which the master latch has a precharge circuit that precharges output terminals to a precharge voltage lower than a supply voltage; and an output circuit that outputs differential output signals to the output terminals in response to differential input signals.
Beneficially, the precharge circuit precharges the output terminals in response to a clock signal of a first state, and the output circuit outputs the differential output signals to the output terminals in response to a clock signal of a second state.
Beneficially, the voltage of the clock signal is lower than the precharge voltage.
Beneficially, the precharge circuit includes a precharge/equalizer circuit that, in response to a clock signal of a first state, precharges the output terminals to the precharge voltage and equalizes the output terminals; and the output circuit includes a differential pair that, in response to the clock signal of a second state, receives differential input signals and outputs first output signals corresponding to the differential input signals, and a CMOS logic circuit that outputs the differential output signals in response to the first output signals.